1. Field of the Invention
The present invention relates in general to charge pump circuits for memory devices, and more particularly to a charge pump circuit for avoiding excessive current which may be generated instantaneously upon application of a supply voltage at an initial operating state, to reduce power consumption and increase reliability in operation.
2. Description of the Prior Art
Generally, a supply voltage is boosted to a desired level to drive memory cells in a memory device. However, the boosted voltage may be dropped due to charge leakage or other conditions. The dropped voltage must be restored to its original level to drive the memory cells accurately. It is common to use a charge pump circuit to restore the dropped voltage to the original level.
Referring to FIG. 1, there is shown a circuit diagram of a conventional charge pump circuit. As shown in this drawing, the conventional charge pump circuit comprises first and second MOS transistors M1 and M2. The first MOS transistor M1 has a gate terminal connected to a word line W/L, a source terminal connected in common to gate and drain terminals of the second MOS transistor M2, and a drain terminal connected to an output terminal Vpp of a pulse generator (not shown) which boosts a supply voltage to a desired level to drive memory cells in a memory device. The second MOS transistor M2 has a source terminal connected in common to the gate terminal of the first MOS transistor M1 and the word line W/L. The drain terminal of the second MOS transistor M2 is also connected to one side of a capacitor C1, the other side of which is supplied with external clock pulses .phi..
The operation of the conventional charge pump circuit with the above-mentioned construction will hereinafter be described with reference to FIG. 1.
When the supply voltage of, for example, 5 V is applied to the memory device to drive the memory cells therein, it is boosted to 15 V (Vpp) by the pulse generator (not shown) of the memory device. The boosted voltage from the pulse generator is applied to the drain terminal of the first MOS transistor M1 in the charge pump circuit. A word line voltage of 5 V is applied to the gate terminal of the first MOS transistor M1, thereby causing the first MOS transistor M1 to be turned on.
As the first MOS transistor M1 is turned on, the word line voltage of 5 V at the gate terminal of the first MOS transistor M1 is transferred to the source terminal thereof, while being dropped by a threshold voltage V.sub.T of the first MOS transistor M1. The resultant voltage (5 V-V.sub.T) at the source terminal of the first MOS transistor M1 is transferred to a node A. Because the node A is connected in common to the gate and drain terminals of the second MOS transistor M2, the voltage (5 V-V.sub.T) thereof is transferred directly to a node B between the drain terminal of the second MOS transistor M2 and the capacitor C1.
Upon receiving the external clock pulse .phi., the capacitor C1 performs a charging operation to generate a voltage .DELTA.V at a rising edge of the clock pulse .phi.. The voltage .DELTA.V generated from the capacitor C1 is added to the voltage (5 V-V.sub.T) at the node B, so that the voltage at the node B is boosted to a level (5 V-V.sub.T +.DELTA.V). The boosted voltage (5 V-V.sub.T +.DELTA.V) at the node B is transferred to the gate terminal of the first MOS transistor M1 and the word line W/L through the source terminal of the turned-on second MOS transistor M2. As a result, the boosted voltage (5 V-V.sub.T +.DELTA.V) appears at the source terminal of the first MOS transistor M1. Namely, the previous voltage (5 V-V.sub.T) at the source terminal of the first MOS transistor M1 is boosted by .DELTA.V. The boosted voltage (5 V-V.sub.T +.DELTA.V) at the source terminal of the first MOS transistor M1 is again transferred to the nodes A and B. In succession, the voltage .DELTA.V is generated from the capacitor C1 at a rising edge of the subsequent clock pulse .phi. and added to the voltage (5 V-V.sub.T +.DELTA.V) transferred to the node B. The resultant voltage at the node B is applied to the gate terminal of the first MOS transistor M1 through the source terminal of the second MOS transistor M2. At that time the voltage at the node A is boosted to 15 V for the last time with the above operation continuously repeated, it is transferred to the word line W/L to drive the memory cells in the memory device.
Noticeably, if a voltage appearing at the drain terminal of the second MOS transistor M2 is 5 V-V.sub.T +.DELTA.V, a voltage appearing at the source terminal thereof must be 5 V-V.sub.T +.DELTA.V-V.sub.T2, where V.sub.T2 is a threshold voltage of the second MOS transistor M2, which results from the voltage at the drain terminal of the second MOS transistor M2 being dropped by the threshold voltage V.sub.T2 thereof. In practice, because the threshold voltage V.sub.T2 of the second MOS transistor M2 is set to "0", the voltage (5 V-V.sub.T +.DELTA.V) at the drain terminal of the second MOS transistor M2 appears directly at the source terminal thereof. Since the voltage (5 V-V.sub.T +.DELTA.V) must be boosted to 15 V, the voltage .DELTA.V generated from the capacitor C1 and the threshold voltage V.sub.T of the first MOS transistor M1 have the following relationship therebetween: EQU V.sub.T &lt;.DELTA.V
However, the above-mentioned conventional charge pump circuit has a disadvantage in that a large amount of current flows instantaneously through the node B between the capacitor C1 and the drain terminal of the second MOS transistor M2 when the clock pulse .phi. is presented to the capacitor C1 as the supply voltage is applied. The instantaneous, excessive current results in unnecessary power consumption and, particularly, latch-up in CMOS transistors.